A liquid crystal display device includes a TFT substrate having thereon a plurality of TFTs (thin-film transistors) and a plurality of pixel electrodes connected thereto arranged in a matrix, an opposite substrate placed opposite to the TFT substrate and having a color filter, a common electrode, and the like formed thereon, and a liquid crystal layer disposed between these opposite substrate and TFT substrate, for example.
Referring to FIG. 24, which is an enlarged cross-sectional view, a configuration of a TFT substrate 100 will be explained. On a glass substrate 101 constituting the TFT substrate 100, a lower layer gate electrode 102, a first base coat layer 103, a semiconductor layer 104, and a gate insulating film 105 are laminated. On the gate insulating film 105, an upper layer gate electrode 106 made of a metallic material is formed, and to cover the upper layer gate electrode 106, a second base coat layer 113 is formed thereover.
On the second base coat layer 113, a first interlayer insulating film 107 and a second interlayer insulating film 108 are laminated in this order. On the surface of the second interlayer insulating film 108, a lower layer gate wiring line 109, an upper layer gate wiring line 110, and a drain wiring line 111 are formed.
In recent years, development of a so-called system liquid crystal, in which a driver circuit and the like are directly incorporated in a glass substrate constituting a TFT substrate has been in progress in an effort to achieve higher functionality and higher integration of liquid crystal display devices. Further, the reduction of a frame region, which is a non-display region around a display region (also referred to as “frame narrowing”) has also been pursued. However, as compared with a semiconductor layer and an insulating film, it is difficult to miniaturize wiring layers, such as gate electrodes and source wiring lines.
Consequently, as shown in FIG. 24, in a region in which the upper layer gate electrode 106 having a larger thickness is formed, the surface of the second interlayer insulating film 108 rises greatly, creating the surface unevenness. Therefore, when the upper layer gate wiring line 110 and the like are patterned by photolithography, the reduction of the accuracy thereof cannot be avoided, and a leakage fault or a wire breakage may be generated in the wiring layer. In a corner portion on the periphery of the raised portion of the second interlayer insulating film 108, for example, because it is difficult to completely remove an unnecessary wiring layer, a residue 112 may remain as shown in FIGS. 24 and 25. A leakage fault between wiring lines is induced by this residue 112. Here, FIG. 25 is a photo showing an enlarged view of the residue 112 formed on the second interlayer insulating film 108.
In this connection, forming a planarizing film on the interlayer insulating film, and then forming a wiring layer on the surface of the planarizing film can be considered. Patent Document 1 discloses performing a planarization of a planarizing film made of a resin and a formation of contact holes in the planarizing film at the same time.
FIG. 26 is a cross-sectional view showing a lamination structure in which a conventional photoresist film 136 is formed. FIG. 27 is a cross-sectional view showing a lamination structure in which a conventional contact hole 138 is formed.
As shown in FIG. 26, on the surface of a semiconductor substrate 131, an SiO2 film 132 is formed. On the surface of the SiO2 film 132, a wiring layer 133 and an oxide film 134 covering this wiring layer are formed. On the surface of the oxide film 134, a polyimide film 139 is laminated.
The oxide film 134 and the polyimide film 139 constitute a planarizing layer 140. By disposing the polyimide film 139 as an upper layer of the planarizing layer 140, the surface unevenness formed on the wiring layer 133 is smoothened.
Further, a photoresist film 136 is formed on the surface of the polyimide film 139. In the photoresist film 136, an opening 137 is formed above the wiring layer 133 by photolithography. Then, by performing etchback using the reactive-ion etching, removal of the photoresist film 136, planarization of the polyimide film 139, and formation of the contact hole 138 are simultaneously implemented as shown in FIG. 27.
After that, other wiring layers are formed on the surface of the polyimide film 139 and inside of the contact hole 138 to connect these other wiring layers to the wiring layer 133.